Kevin Huang Ph.D. Defense (Mon Dec. 15, 2pm, CIS-X 101)

Come for some food if still around next Monday!

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Title: Expandable Monolithic Silicon Network For Cost-Effective Large Area Electronics

University Oral Examination
Kevin Huang
Department of Electrical Engineering
Stanford University
Advisor: Peter Peumans

Date: Monday, December 15, 2008
Time: 2pm (Refreshments served at 1:45pm)
Location: CIS-X 101 (Auditorium)

Abstract:

CMOS technology has progressed substantially over the past decades in terms of cost per function and energy required per unit of computation due to advances in microelectronic manufacturing.  Unfortunately, these advances have not been shared by the field of large area electronics because a different set of constraints exists in this field, for example, cost per unit area is an important factor when evaluating the applicability of technologies.  Therefore, entirely different technologies such as inkjet printing or other pattern transfer methods are used. One method, fluidic self-assembly, uses small chiplets of monolithic silicon electronics that self-assemble at specific sites in a large-area system to realize large-area electronics. This approach does benefit from advances in CMOS technology and allows one to build large-area and high-performance electronic systems, but it has proven challenging to ensure high yields and throughput. 

Our approach to construct large-area electronic systems from monolithic silicon substrates expands a functional silicon die by several orders of magnitude in area by structuring the silicon die as a two-dimensional network of silicon islands and springs.  Each island houses electronics and connects mechanically and electrically via springs to neighboring islands in a 2D network topology. Electrical interconnects on top of the spiral springs provide electrical connectivity between the islands. Since all the strain induced by the expansion process is contained in the spiral springs, the active device area remains strain free.  Silicon networks with built-in 2D expandability can also conform to curved surfaces.  The fabrication process required to realize such networks can be performed on a wafer that has been fully processed in a foundry as a post-CMOS process.

Expandable silicon is a platform technology that enables the use of microelectronic manufacturing, with its exponential reduction in cost per electronic function and exponential increase in performance, in large-area systems. This preserves the benefits of foundry processing while reducing cost per unit area to levels compatible with many application domains.  This technology can be used for the cost-effective manufacturing of microconcentrator solar cells, RFID tags, sensor networks, curved imagers, retinal prostheses, and displays. In my talk, I will discuss the design constraints of expandable silicon, the processes that were developed and illustrate the use of expandable silicon.